The Truth About The

Datalink GW1000

The Datalink GW1000

Does Not Meet Allen-Bradley Specifications
Looking at the oscilloscope captures of a DH+ network below, one can easily see that the Datalink GW1000 has sub-standard signal levels.

Image 1: DH+ Network with No Load

Image 2: DH+ Network with 100 Ohm Load

Image 3: DH+ Network with 51 Ohm Load

Image 4: DH+ Network with 10 Ohm Load

In each of the above, three Allen-Bradley devices, one Equustek DL3500 and the Datalink GW1000 are shown communicating on a DH+ Network. Four different load conditions are tested, and are summarized below:

Table: Peak-to-Peak Voltage of the DH+ port under different load conditions

The load values were chosen to emulate realistic situations. Allen-Bradley recommends two 150 ohm resistors, one at each end of the transmission line to reduce reflections. (See Ref Allen Bradley 1770-um022-en-p.pdf). The recommended Belden 9842 ‘Blue Hose’ cable (See, has a capacitance of 12.8 picofarads per foot, so 10,000 feet at 57,600 Hz represents an impedence of 22 ohms.

This summary indicates that the Datalink GW1000 transmits with less than one half the power of the other devices with no load and only about one ninth of the power of the other devices under a heavy load.

What does this mean to the user of the Datalink GW1000?
  1. The user cannot rely on the Datalink GW1000 to meet the Allen-Bradley distance versus baud rate specifications.
  2. Error rates are a function of signal power and noise power. Clearly the Datalink GW1000 is less resistant to noise induced errors than other devices.
  3. CRC (cyclic redundancy codes) can detect many errors, but not all errors.
  4. Any undetected error, even a single bit, in a process control system can have disastrous consequences.

About Data Highway Plus (DH+)

A DH+ link is optimally used for smaller networks consisting of limited nodes (about 15 maximum). A DH+ link accepts 64 devices and can transmit data at 57.6, 115.2, or 230.4K bits. (PLC-5/250, SLC, and PLC processors support 57.6 and 115.2K bits; SLC 5/04 processors support 230.4K bits; PLC-5 processors are expected to support 230.4K bits early in 1997.)
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